Real-time FPGA Design for OMP Targeting 8K image Reconstruction

Corresponding author
Hosei University
MMM 2022

Abstract

Due to hardware limitations in sampling, we begin our work with a deterministic matrix. We employ a sparse sensing matrix capable of achieving high-quality results. Utilizing sparsity, we streamline calculations in each iteration, replacing complex operations with simpler procedures.

This implementation is carried out on the Xilinx Virtex UltraScale+ FPGA device. Experimental results demonstrate a speedup of 290 times compared to the state-of-the-art method, requiring only 0.026 seconds to reconstruct an 8K grayscale image, achieving real-time reconstruction at 30 FPS.

Motivation

DDNeRF_Architecture_v21

Top: The architecture of PGTformer.

Methods

DDNeRF_Architecture_v21

Top: The architecture of PGTformer.

Experimental Results

DDNeRF_Architecture_v21

Quantitative comparison on VFHQ Blind setting.

BibTeX


  @inproceedings{xu2022real,
  title={Real-time fpga design for omp targeting 8k image reconstruction},
  author={Xu, Jiayao and Fu, Chen and Zhang, Zhiqiang and Zhou, Jinjia},
  booktitle={International Conference on Multimedia Modeling},
  pages={518--529},
  year={2022},
  organization={Springer}
}